Semiconductor industry

Semiconductor manufacturing in the mid-2020s is defined by two parallel stories: ever-smaller silicon nodes (3nm and 2nm) and the rising importance of materials, packaging, and supply-chain logistics that sit outside the fab itself.

Leading-edge economics

A new advanced fab costs on the order of 15 to 20 billion USD. High-NA EUV tools run 350 to 400 million each. Wafers at 3nm commonly land in the 20,000 to 25,000 USD range; full mask sets and chip design budgets reach hundreds of millions to over one billion. Early yields at new nodes often start near 50–60% before maturing toward 70–80%. Profitability depends on volume and utilization, not just technical success.

Beyond Moore on silicon

Wide-bandgap semiconductors (SiC, GaN) dominate high-voltage power and RF switching where silicon efficiency plateaus. Advanced packaging — CoWoS for AI accelerators, ABF build-up substrates, 3D die stacking — has become a capacity constraint as important as lithography for high-end compute.

Supply chain and structure

Foundry production is highly concentrated. Export controls, equipment lead times, and long material qualification cycles mean substitutions are slow. The industry splits into fabless design (high margins, foundry-dependent), pure-play foundries (capital-intensive, utilization-driven), and IDMs that must fund both R&D and fab scale.

The chapter notes below walk through fabrication stages, substrate physics, lithography, packaging economics, and geopolitical risk — with linked research, media, and supply-chain data for the names we cover.

The semiconductor manufacturing process is an intricate sequence of chemical, physical, and photographic steps that transforms raw elements, primarily silicon, into highly advanced integrated circuits (ICs) The entire procedure demands extreme precision, specialized equipment, and ultra-high purity materials, and can take up to 26 weeks from design to final production
This process is generally divided into six major stages:
1. Wafer Preparation and Fabrication

The foundation of any semiconductor device is the silicon wafer. The process begins with a pure silicon crystal, known as an ingot, which is sliced into ultra-thin wafers These wafers undergo meticulous cleaning and polishing to create a flawlessly smooth, mirror-like substrate, as even microscopic contamination or scratches can lead to product defects Generally, the first processing step involves thermal oxidation—heating the wafer in a furnace (often up to 1200ºC) with oxygen or steam to grow a thin, protective layer of silicon dioxide (SiO_2) on the surface to act as an insulator
2. Photoresist Coating and Photolithography (Patterning)

To transfer the intricate microchip design onto the silicon, the wafer’s surface is coated with a light-sensitive liquid called a “photoresist.” The wafer is spun at high speeds to ensure a thin, uniform coating across the entire surface Positive photoresists, which become soluble and dissolve when exposed to light, are the most commonly used type due to their superior resolution and thermal stability After a “soft bake” to cure the resist and evaporate solvents, the wafer moves to the crucial photolithography stage A photomask containing the circuit blueprint is precisely aligned over the wafer, and ultraviolet (UV) light is projected through it, transferring the circuit pattern directly onto the photoresist
3. Etching and Stripping

Once the pattern is projected, the unnecessary materials on the wafer (such as excess SiO_2, metals, or polysilicon) are removed to form the device’s micro-architecture This is accomplished through two primary methods:

• Wet Etching: Submerging the wafer in specific chemical acid baths to dissolve material
• Dry Etching: Using reactive gases or plasma (such as reactive ion etching) to bombard the wafer, offering superior precision for modern, high-density circuits 15-17.After etching, the remaining photoresist is stripped away. This is often done using “plasma ashing,” where oxygen radicals oxidize the resist into vapor, followed by chemical rinses to leave the etched pattern completely clean

4. Doping (Junction Formation)

To give the pure silicon its actual “semiconducting” properties, specific impurities must be introduced to alter its electrical conductivity, creating either p-type (positive, using elements like boron) or n-type (negative, using elements like phosphorus or arsenic) regions This is done through two primary techniques:

• Diffusion: Heating the wafer in a furnace (1000-1250ºC) and introducing a dopant gas, allowing atoms to naturally migrate into the silicon
• Ion Implantation: Stripping dopants of their electrons and using a high-current accelerator to fire the ionized particles directly into the crystal lattice of the wafer 21, 22.Because ion implantation can damage the silicon lattice, the wafer is subjected to a high-temperature thermal annealing process to repair the crystal structure and fully activate the embedded ions

5. Deposition

To build the complex, multi-layered, three-dimensional architecture of a modern microchip, thin films of conductive, semiconducting, and insulating materials are deposited onto the wafer Major deposition techniques include:

• Chemical Vapor Deposition (CVD): Reacting specific source gases in a heated chamber to deposit uniform solid layers of materials like silicon nitride or polycrystalline silicon
• Physical Vapor Deposition (PVD) & Atomic Layer Deposition (ALD): Used to apply exceptionally precise, ultra-thin films
• Epitaxy: Growing a new, thin elemental crystal layer directly on top of the original substrate 27.Because chips feature dozens of vertical layers, the photolithography, etching, and deposition steps are continuously repeated for every single layer until the full circuit is built

6. Assembly, Testing, and Packaging (ATP)

The final stage transforms the completed wafer into usable consumer components. The wafer is separated (diced) into individual chips These individual chips, or dies, are attached to specialized substrates and encased in a functional, protective metallic or plastic housing featuring a cooling system to prevent overheating
Modern packaging has moved far beyond simple protection. Advanced packaging innovations—such as 3D stacking, fan-out packaging, and System-in-Package (SiP)—are now heavily relied upon to combine multiple functional dies into a single package, vastly reducing footprint while boosting performance and energy efficiency

As the demands of modern electronics push the boundaries of power, temperature, and high-frequency performance, traditional silicon (Si) is reaching its physical limitations 1-3. To build smaller, faster, and more efficient systems, the industry is increasingly turning to wide-bandgap (WBG) compound semiconductors—primarily Silicon Carbide (SiC) and Gallium Nitride (GaN)
The Science of the Bandgap

A “bandgap” is the amount of energy required to release electrons in a semiconductor material so they can move freely and conduct electricity It represents the energy difference between the top of the valence band (where electrons are bound) and the bottom of the conduction band 6-8.
While silicon has a bandgap of 1.12 eV, SiC and GaN have much wider bandgaps of approximately 3.26 eV and 3.4 eV, respectively 9-11. This wider bandgap provides them with a dielectric breakdown field strength almost ten times higher than that of silicon Consequently, WBG devices can sustain much higher voltages with active layers that are a fraction of the thickness of silicon, drastically lowering energy losses
Silicon Carbide (SiC): The High-Power Workhorse

SiC is a compound of silicon and carbon characterized by its incredibly robust thermal and high-voltage properties

• Thermal Conductivity: SiC excels at dissipating heat. It features a thermal conductivity of 4.9 to 5 W/cm·K, which is more than three times better than silicon
• Key Applications: Its ability to operate reliably in high-temperature environments (>200ºC) and manage high voltages (ranging from 600V up to 3.3kV) makes SiC the ideal choice for heavy-duty applications. This includes electric vehicle (EV) traction inverters, solar and wind renewable energy systems, railway traction, and industrial motor drives 15-18.
• Challenges: SiC wafers are complex and expensive to manufacture The material requires very high temperatures and significant time for crystal growth, and finding surface defects can be exceptionally difficult due to the material’s transparency and hardness

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Gallium Nitride (GaN): The High-Frequency Champion**GaN is a compound of gallium and nitrogen that dominates in high-speed, high-frequency operations

• Electron Mobility: The defining advantage of GaN is its exceptionally high electron mobility (2000 cm²/Vs), which allows electrons to move over 30% faster than in silicon This enables GaN devices to switch at megahertz (MHz) or even gigahertz (GHz) frequencies
• Key Applications: GaN’s incredible switching speeds and power density make it perfect for miniaturized power systems. It is heavily utilized in 65W/100W fast chargers, 5G/6G communication towers, radar systems, and RF amplifiers 16, 24-26. Furthermore, GaN is the foundational material for blue LEDs, lasers, and modern energy-saving white lighting
• Challenges: GaN has a lower thermal conductivity (1.3 to 2.5 W/cm·K) than SiC, which generally limits its use to lower-voltage applications (typically \<650V) Because growing pure GaN wafers is notoriously difficult and expensive due to crystal defects, manufacturers often grow thin GaN active layers on top of standard silicon substrates to keep costs down 29-31.

As the semiconductor industry pushes toward smaller transistor geometries, such as the 3nm node, the economic and technical barriers to entry have skyrocketed. Building a modern fabrication plant (fab) is a massive financial undertaking, with advanced chip manufacturing costs requiring billions of dollars in capital expenditure 1-3.
The Staggering Costs of Modern Fabs

The high costs of 3nm manufacturing are driven by the need for ultra-specialized cleanroom facilities, immense energy consumption, and the high salaries of specialized engineering talent Furthermore, the equipment required to achieve these microscopic nodes is incredibly expensive. As a result, the global tech supply chain has become a highly competitive arms race, resulting in tightening 3nm capacity among top foundries
The Role of High-NA EUV Lithography

A critical factor in next-generation fabrication is Extreme Ultraviolet (EUV) lithography. To print even smaller and denser features, the industry is transitioning to High-NA (Numerical Aperture) EUV systems, developed by companies like ASML and ZEISS High-NA EUV provides the superior resolution necessary for future chip generations by utilizing advanced mirroring technology
However, this cutting-edge equipment comes with eye-watering price tags. The cost is so prohibitive that even industry leaders like TSMC have historically weighed the economic feasibility of adopting High-NA EUV equipment against their existing production techniques, leading to strategic decisions about when to integrate these expensive machines

As traditional Moore’s Law slows down, the industry can no longer rely solely on shrinking transistors to improve performance. Instead, the focus has shifted to the “back-end” of manufacturing: advanced packaging
The Shift to Chiplets and Heterogeneous Integration

Instead of manufacturing one monolithic chip, companies are now designing “chiplets”—discrete, unpackaged dies that are each optimized for a specific function and manufactured on the most suitable node These chiplets are then assembled together in a single package using heterogeneous integration techniques This process is largely handled by OSATs (Outsourced Semiconductor Assembly and Test companies), which have become crucial players in the value chain
The CoWoS Bottleneck

For high-performance AI processors, advanced packaging is the new chokepoint For example, a $40,000 Nvidia AI GPU is heavily dependent on TSMC’s proprietary CoWoS (Chip-on-Wafer-on-Substrate) packaging technology The immense demand for AI chips has caused a severe tightening in CoWoS capacity, turning it into an invisible bottleneck for the entire AI industry
The ABF Substrate Vulnerability

Another critical failure point in the IC packaging supply chain is Ajinomoto Build-up Film (ABF) Originally developed by the food and seasoning company Ajinomoto, ABF is a specialized microfilm used for interlayer insulation in high-performance processors This niche material is absolutely essential for semiconductor packaging, and any shortages in ABF substrate manufacturing severely limit the global output of advanced microchips

The semiconductor supply chain is highly globalized, making it acutely vulnerable to geopolitical tensions, trade wars, and natural resource constraints.
China’s Critical Mineral Export Controls

China holds significant dominance over several critical minerals required for semiconductor manufacturing To exert strategic pressure, China has utilized export controls and restrictions on vital elements like gallium, germanium, and antimony 19-21. Because these materials are foundational for legacy chips, optics, and wide-bandgap semiconductors, these restrictions heavily impact global markets and force Western nations to urgently seek alternative supply chains
Middle East Conflicts and the Photoresist Supply

Geopolitical risks extend beyond US-China tensions. For example, conflicts in the Middle East—particularly involving Iran and the Strait of Hormuz—pose a direct threat to the semiconductor materials market Japanese companies dominate the global supply of photoresists, the light-sensitive chemicals used in lithography However, the production of these photoresists relies heavily (over 40%) on naphtha solvent imported from the Middle East Consequently, disruptions in the Strait of Hormuz can cause solvent shortages, triggering a cascading crisis for major chipmakers like Samsung and SK Hynix
The Looming Water Crisis

Beyond geopolitics, the industry faces a severe environmental constraint: water. Semiconductor manufacturing requires massive quantities of ultra-pure water to clean wafers between the hundreds of chemical and etching steps Projections indicate that water usage in semiconductor manufacturing will double by 2035 Managing this immense water demand is becoming one of the most pressing sustainability challenges for foundries worldwide

While Chapter 4 introduced the capacity constraints of advanced packaging like CoWoS, the true underlying limitation for future AI accelerators is a combination of optical geometry and mechanical physics. As AI architectures demand increasingly larger packages, the industry is hitting physical walls that cannot be solved simply by adding more traditional equipment.
The Reticle Limit and Edge Scrap

The foundation of the modern packaging bottleneck is the “reticle limit.” This is the absolute maximum area a lithography machine can project light onto a wafer in a single pass, which tops out at approximately 858 square millimeters due to the physics of focusing light through lenses For context, the silicon engine driving the AI boom, Nvidia’s H100 die, is 814 square millimeters By placing that die inside the 858 mm boundary, it becomes mathematically clear that monolithic processors have hit a physical wall and cannot grow much larger
To build larger systems, manufacturers must stitch multiple chiplets together on a single package. However, mapping massive, rectangular chip packages onto a standard circular 300mm silicon wafer creates vast amounts of unusable space known as “edge scrap” As package sizes inflate, edge scrap destroys area utilization economics and consumes a larger share of wafer capacity
Mechanical Physics Failures and the CTE Mismatch

Beyond geometry, packaging massive AI chips introduces severe thermodynamic and mechanical challenges. During the high-temperature baking and deposition steps of packaging, the different materials in the chip (such as the silicon die versus the organic or glass substrates) expand and contract at different rates
This difference, known as the Coefficient of Thermal Expansion (CTE) mismatch, generates immense mechanical stress The stress causes structural warpage, which can physically snap or delaminate the microscopic redistribution layers (RDL) connecting the chips A single microscopic crack caused by this warpage instantly destroys a 40,000 AI chip These severe thermodynamic yield issues are the direct cause of the massive delivery delays currently affecting the enterprise hardware market
The Escape Route: Panel-Level Packaging (PLP / CoPoS)

To bypass the constraints of circular wafers and edge scrap, the industry is racing toward Panel-Level Packaging (PLP), such as TSMC’s upcoming CoPoS technology This involves shifting from a 300mm circular wafer to a massive 515x510 mm rectangular panel
By using rectangular panels, manufacturers achieve a perfectly optimized grid with zero edge scrap, dramatically changing the physical limits of heterogeneous integration and allowing for far more complex AI architectures However, this transition abandons decades of circular wafer standards and introduces an entirely new engineering nightmare: managing extreme thermal warpage on a glass or organic panel the size of a television screen without breaking the delicate chips inside

As chip architectures push toward the 3nm node and below, the resources required to build them have skyrocketed. The semiconductor industry is facing an unprecedented resource crisis, sitting squarely at the nexus of massive energy consumption, severe water demands, and geopolitical expansion.
The Immense Energy Cost of 3nm Fabs

Running a 3nm semiconductor fabrication plant pushes power consumption to unprecedented levels Extreme Ultraviolet (EUV) lithography scanners, which run 24/7, require several megawatts of power to operate When combined with the massive air handling systems, liquid cooling solutions, and uninterrupted power supplies (UPS) needed to maintain perfect cleanroom environments, a single 3nm wafer requires approximately 500 kWh of electricity to process Consequently, the annual power cost for a single advanced 3nm fab can easily reach 100 million to 300 million
The Ultra-Pure Water (UPW) Crisis

Water is equally critical. Semiconductor manufacturing uses water to aggressively rinse wafers between hundreds of etching and chemical-mechanical planarization (CMP) steps to remove microscopic contaminants This process requires Ultra-Pure Water (UPW). Generating UPW is highly inefficient; it takes roughly 1,400 to 1,600 gallons of municipal water to produce 1,000 gallons of UPW
A single 3nm wafer can consume between 1,500 and 2,000 gallons of UPW In 2023 alone, TSMC consumed a staggering 101 million cubic meters of water With global semiconductor water usage projected to double by 2035, the industry faces a severe geographical risk: approximately 40% of existing and planned fabs are located in areas projected to face high or extremely high water stress by 2030, including hubs in Taiwan and Arizona
Reclamation, Desalination, and the Energy Trade-Off

To combat this, the industry is turning to utility-scale water infrastructure:

• Recycling: Fabs are targeting >70% water recycling rates TSMC is building a 15-acre reclamation plant in Arizona to recycle up to 90% of its wastewater, while Intel recently partnered to build the Ocotillo Brine Reduction Facility to add 11 million liters of treatment capacity to its Arizona campus
• Desalination: Taiwan is investing €508 million into a seawater desalination plant to secure water for the Hsinchu Technology Park 16.However, treating and desalinating water is extraordinarily energy-intensive This creates a difficult negative feedback loop: solving a fab’s local water constraints directly exacerbates its local electrical grid constraints

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The Complexities of Geographic Diversification**Driven by the vulnerabilities of concentrating 90% of advanced manufacturing in Taiwan, governments have introduced the U.S. CHIPS Act (52.7 billion) and the European Chips Act (46 billion) to incentivize reshoring
Despite these massive capital injections, expanding advanced fabs globally (such as TSMC’s 165 billion commitment in Arizona) faces profound hurdles The U.S. lacks the highly dense, specialized, and deeply integrated local supplier ecosystem that exists in Taiwan Furthermore, significant cultural and work-philosophy differences between American engineering teams and the highly rigid, execution-focused culture of pure-play foundries have caused notable operational friction and project delays Ultimately, building a resilient global supply chain requires more than just pouring concrete; it requires replicating decades of localized chemical, material, and talent ecosystems